I. Field of the Disclosure
The technology of the disclosure relates generally to pulse signal generation, and particularly to generating pulse signals for pulse latches with minimum hold time.
II. Background
Digital logic circuits include devices for storing state information of data bits at various points in corresponding data paths. Different types of devices for storing state information exist, each possessing certain unique features. For example, master-slave flip-flops (MSFFs) are conventional devices employed to store state information of data bits in a digital logic circuit. MSFFs are two-stage devices configured to stabilize state information of a data bit for a particular setup time prior to an active transition of a clock signal, and provide the state information in response to a clock signal transitioning to an active state. The setup time of an MSFF may limit the performance of delay-sensitive digital logic circuits. In this manner, other devices having no setup time can be employed to avoid the performance limitations attributable to the setup time of MSFFs. For example, pulse latches are devices that store state information of data bits without a setup time. More specifically, pulse latches are devices configured to transfer state information of a data bit from an input to a storage element and an output in response to an active transition of a clock signal without the need for a setup time to stabilize the input signal.
In this regard, FIG. 1 illustrates a conventional pulse latch 100 that is clocked by a conventional pulse generation circuit 102. The conventional pulse latch 100 is configured to store state information of an input signal 104 and provide the stored state information via an output signal 106 in response to a pulse signal PULSE. For example, the input signal 104 is provided to an inverter 108, which provides an inverted input signal 110 to a transmission gate 112. In response to the pulse signal PULSE being in an active state (and an inverted pulse signal PULSE_B being in an inactive state), the transmission gate 112 provides the inverted input signal 110 to cross-coupled inverters 114, 116 and an inverter 118. Additionally, the pulse signal PULSE being in an active state deactivates a transmission gate 120, which disconnects the cross-coupled inverters 114, 116. In this manner, the inverted input signal 110 is reflected through the transmission gate 112, while the inverter 118 provides the state information via the output signal 106. In response to the pulse signal PULSE being in an inactive state, the transmission gate 120 is activated and couples an output of the cross-coupled inverter 116 to the inverter 118, thus causing the state information to be held on the output signal 106 while the conventional pulse latch 100 is not being clocked by the pulse signal PULSE. The pulse signal PULSE is generated by the conventional pulse generation circuit 102 in response to a clock signal CLK transitioning to an active state. In this manner, because the state information is provided to the cross-coupled inverters 114, 116 and to the inverter 118 in response to an active transition of the clock signal CLK, the conventional pulse latch 100 does not incur a setup time to stabilize the input signal 104 prior to transferring the state information for storage.
Although the pulse latch 100 does not incur a setup time, storing the state information in the pulse latch 100 requires the input signal 104 to remain stable for a particular hold time while the state information is provided to the cross-coupled inverters 114, 116 and the inverter 118. However, the hold time needed for stability may vary based on process, voltage, and temperature (PVT) variations of elements in the pulse latch 100. Further, as a supply voltage used to drive the elements of the pulse latch 100 decreases to reduce power consumption, the effect of PVT variations on elements of the pulse latch 100 increases, which causes the hold time needed for the pulse latch 100 to vary. For example, if the supply voltage is decreased to a near threshold voltage (NTV), the hold time of the pulse latch 100 can vary in response to PVT variations present during a particular operation. In order to account for such hold time variations, the number N of inverters 122(1)-122(N) (N being any odd integer) employed in the pulse generation circuit 102 are increased to provide the pulse signal PULSE with a pulse width corresponding to a worst-case hold time of the pulse latch 100 to account for the PVT variations. However, increasing the number N of the inverters 122(1)-122(N) increases the hold time, thus reducing the performance of the pulse latch 100.